Ultra-low power dissipation is required of a driver IC for a mobile display, such as a mobile telephone terminal. In actual application, such mobile display is mostly in idle mode. Hence, a demand for reducing the power dissipation in such idle mode is stringent.
In mobile displays, in the idle mode, image is not displayed with full-color mode (full grayscale display with preset plural bits each for R, G and B) but with eight-color mode (display with one bit each for R, G and G). In the eight-color display mode, a source driver that drives a source line, is not an analog buffer, but a buffer using an inverter which drives a source line based on 1-bit data for each of R, G and B color data. In case the buffer used is a non-inverting buffer, it is made up of two cascaded inverters.
In Patent Document 1, there is disclosed a TFT-LCD and a method for driving the device through multi-stage charge re-utilization as the configuration for reducing power dissipation of a display. This TFT-LCD includes a recovering capacitor (external capacitor) connected between a source driver (source driving unit) and a liquid crystal panel. The capacitor operates for recovering electric charge on a source line which is at a higher voltage than that of a common electrode when it is connected to the source line connection and for supplying charge to a source line which is at a lower voltage than that of the common electrode. The TFT-LCD further reduces the power dissipation in accordance with a driving scheme which is based on re-utilization of pre-existing charge.
FIG. 10 is a diagram illustration the configuration of the invention disclosed in Patent Document 1. It should be noted that FIG. 10 is a re-formulation by the present inventor of the drawing of Patent Document 1 for ease in understanding its technical contents. Referring to FIG. 10, showing eight-color display for the idle mode, with two values by one-bit data for each of R, G and B, a source buffer (source driver) 108, driving a source line, is not an analog buffer, but a tri-state buffer, driving the source line based on 1-bit data for each of R, G and B color data. In more detail, the source buffer 108 is a tri-state buffer made up of an initial-stage buffer and an inverter having its output enable/disable controlled by a recovery clock 105. When the recovery clock 105 is on, such as HIGH in level, an output of the source buffer 108 is in HI-Z state (in a high impedance state), while a recovery switch 110 is turned on to store electric charge on the source line in a recovery capacitor 112. When the recovery clock 105 is then turned off, such as LOW in level, the recovery switch 110 is turned off to set an output enable state of the source buffer 108 to charge the source line from the source buffer 108. In FIG. 10, the part shown above pads 113 is for a display controller, also called a display control driver or a control IC, and the part shown below the pads 113 is for a display panel (LCD panel). The capacitors connecting to the source lines of the display panel are represented by pixel capacitances as equivalent circuits. The source driver (source buffer) and the source line are also referred to as a data driver and a data line, respectively.
FIG. 11 shows the configuration disclosed in Patent Document 2. It should be noted that FIG. 11 represents re-formulation by the present inventor of the drawing of Patent Document 2 for ease in understanding its technical contents. Referring to FIG. 11, there is provided a COM buffer 118, and the output of the COM buffer 118, as a common electrode, is recovered by the recovery capacitor. In the configuration of FIG. 11, charges on source lines S1 to S3 and on the common electrode are recovered simultaneously. Meanwhile, in the configuration of FIG. 11, a capacitance of the common electrode (COMMON electrode), connecting to a pad 120, is used as a capacitance in which to store recovered electric charge.
FIG. 12 shows the configuration disclosed in Patent Document 3, which comprises a current line data latch circuit for holding color data of the current line, a previous line data latch circuit for holding color data of a previous line, and a switching controller for controlling a recovery switch from the color data of the previous and current lines and from the recovery clock. Regarding the source line SI, a switching controller 541 operates as follows only when the outputs of a current line data latch circuit 551 differ from those of a previous line data latch circuit 451. The switching controller 541 operates: in response to an output of the previous line data latch circuit 451 to turn on a one of switch for high voltage (transfer gate) 411 and a switch for low voltage (transfer gate) 421, while operating in response to an output of the previous line data latch circuit, transferred from the current line data latch circuit 551, to turn on the other of the switch for high voltage (transfer gate) 411 and the switch for low voltage (transfer gate) 421, thereby connecting the source line SI to a capacitor for high voltage (recovery capacitor for high voltage) 431 or a capacitor for low voltage (recovery capacitor for low voltage) 432. In a source line where the applied voltage is changed with time, electric charge are stored or furnished effectively, decreasing the power dissipation. On the other hand, in a source line where the applied voltage remains unchanged, the voltage retained remains unchanged, so that there is no power dissipation when the voltage is next applied.
FIG. 13 is a timing chart for illustrating the operation of the constitution shown in FIG. 12. In displaying an N'th line, a control signal for a pixel switch is activated to connect a source line in a display controller and a source line on a display panel. The source line SI, on which the output of the previous line data latch circuit 451 is “0” and the output of the current line data latch circuit 551 is “1”, is connected to the capacitor for low voltage 432, and then connected to the capacitor for high voltage 431, by the HIGH of the recovery clock. A voltage C is then written on the source line S1 by a D/A converter 311. The source line S2, on which the output of a previous line data latch circuit 452 is “1” and the output of a current line data latch circuit 552 is “0”, is connected to the capacitor for high voltage 431, and then connected to the capacitor for low voltage 432, by the HIGH of the recovery clock. A voltage C is then written on the source line S2 by a D/A converter 312. In displaying an (N+1)st line, the operation is reversed from that in displaying the N'th line, that is, the source line S1 is changed over from the high voltage to the low voltage, while the source line S2 is changed over from the low voltage to the high voltage. Hence, it is verified, based on color data on the previous and current lines, whether or not recovery is to be made, in order to control the recovery operation.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-22329A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2002-244622A
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-P2003-271105A